1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device.
2. Related Art
In recent years, as miniaturization of LSIs has progressed, insulating films having a low specific dielectric constant have been chiefly used as interconnect insulating interlayers. In addition, cap insulating films which are etching stoppers have been thinned for the purpose of the low-dielectric constant. Thereby, the etching stop property remarkably decreases in a process of forming via interconnects. Further, it is required to introduce slit-shaped vias having a large opening diameter in order to reduce the via resistance. For this reason, in LSI interconnects in the future, there will be increased importance for a technique for simultaneously processing a normal via and a slit-shaped via having a larger diameter than that of the via.
Such a technique for forming slit-shaped via patterns having different opening diameters is disclosed in, for example, Japanese Unexamined Patent Publication 2007-318124.
Japanese Unexamined Patent Publication 2007-318124 discloses that in an insulating interlayer of SiCOH provided on a cap insulating film of SiCN, an etching stopper in the slit-shaped via pattern portion having a large opening diameter is partially thickened. Thereby, it is disclosed that variation in the depth between vias can be suppressed by increasing the etching stop property. In addition, gaseous species are not disclosed in Japanese Unexamined Patent Publication 2007-318124.
Meanwhile, Japanese Unexamined Patent Publication 2009-105272 discloses a technique for controlling the etching rate of trenches having different aspect ratios. That is, Japanese Unexamined Patent Publication 2009-105272 discloses that the trench is formed in a CF-based insulating interlayer provided on a cap insulating film such as SiC, by combination use of hydrogen-containing gas such as CH3F gas and N2 gas. In the trench forming process, in a via hole having a small aspect ratio, a deposit is deposited at the bottom.
On the other hand, in a via hole having a high aspect ratio, a deposit is not deposited at the bottom. For this reason, it is disclosed that in the via hole having a small aspect ratio, the etching rate can be reduced by the deposit.
On the other hand, a technique for improving the etching stop property of the cap insulating film is disclosed in, for example, Japanese Unexamined Patent Publication 2008-177596. In Japanese Unexamined Patent Publication 2008-177596, plasma processing is performed on the insulating interlayer of (HO)3SiCH3 provided on the cap insulating film of SiN, by replacing O2 gas with N2 gas in mixed gas of CF gas/O2 gas/Ar gas. It is disclosed that since the N2 gas cannot chemically etch a CF-based deposited film, the drawing-out phenomenon of CH3 of the insulating interlayer in which the CF-based deposited film exists does not occur. Thereby, it is disclosed that the selectivity to SiN is raised while the generation of a sub-trench is suppressed.
In addition, M. Ueki, IEEE, pp 619-622 (2008) discloses that etching damage can be suppressed using a high carbon-containing organic silica film. As shown in M. Ueki, IEEE, pp 619-622 (2008), the carbon content of this high carbon-containing organic silica film is higher than the carbon content of a porous SiOCH film generally widely used as shown in Japanese Unexamined Patent Publication 2007-318124.